Project conclusion

Organic thin film transistors produced by nanoimprint lithography (NIL) hold a particularly high promise for applications in integrated circuits due to their small channel lengths and therefore possible fast switching speed. 


The characteristics of organic thin film transistors (OTFTs) are crucially determined by the properties of the interface between the organic semiconductor and the metal electrodes as well as the gate dielectric. The interface properties influence parameters such as the carrier trap density, the charge carrier concentration (by local doping), or the local field distribution (if polar groups are present at the interface). Moreover, when decreasing the channel length to less than a µm, as aimed at when applying NIL, the contact resistance plays an ever increasing role. The latter is determined by the film morphology, but also by the carrier injection barrier. These parameters can be controlled by appropriately adjusting the properties of the interface between the organic layer and the electrodes. In OTFTs based on small molecules, also the morphology of the semiconductor plays a crucial role. The morphology, being defined during the initial stages of film growth, depends to a large extent on the dielectric/semiconductor interface. 
Therefore, substrates with a smooth and trap-free dielectric surface with suitable surface energies are highly desirable. In this context, several priming layers and pre-treatment methods of the interface dielectric layer and the gold electrodes have been investigated with respect to semiconductor grain size and transistor performance. 


Within the NILsimtos sub-μm OTFTs are fabricated by Hot Embossing Nanoimprint Lithography (HE-NIL) of the source/drain electrode on pre-structured gates and gate dielectrics. The channel lengths of the transistors vary between 400 and 2400 nm (stamp size), but also concepts for a further reduction in channel length down to 200 nm were evaluated. OTFTs were fabricated with different dielectric layers like SiO2, ZrO2-PVCi nanocomposite, BCB or Ormocere® and in different device setups. The electrical characteristics of numerous OTFTs were used to verify critical OTFT parameters like contact resistance, charge carrier injection barrier, onset/threshold-voltage, interface trapping and charge carrier mobility by device modeling. 


One of the most critical issues in NIL-fabricated OTFTs is the charge injection barrier from the gold source/drain electrodes into the organic semiconducting layer. Compared to the most common OTFT setup as reported in literature, where the gold electrode is evaporated onto the semiconducting layer through a shadow mask, the deposition of the organic semiconductor in NIL-fabricated devices is the last process step. Due to surface contaminations of the gold electrode after the wet chemical lift-off step the work function is  reduced resulting in a higher charge carrier injection barrier. To achieve a lower charge carrier injection barrier a modification of the gold source-drain electrodes by a UV-ozone treatment turned out to be the most efficient method. The chemical and electronic modification of the electrode by ozone pre-treatment was studied and optimized by surface analysis methods like x-ray- and UV-photoelectron spectroscopy (XPS, UPS).


Particular attention was paid to the influence of the interface between the gate dielectric and the active material; several interface modification approaches were tested. By modifying the dielectric layer by photo-reactive polymers or self-assembled monolayers (SAMs) a significant shift in the OTFTs onset voltage could be achieved. The idea behind these modifications is the alignment of voltage levels in future organic electronic circuits. This method was already demonstrated within this project for an organic inverter. 


As a main objective in this project a profound theoretical description of the charge carrier transport was performed by a drift-diffusion based model combined with a Poisson equation. The model allows the incorporation of electric field strength- and carrier density-dependent mobilities, the carrier generation/recombination from deep trap states within the band gap and injection barriers at the contact interfaces. Thus, a deeper insight to critical parameters in the device setup for further improvement of device performance is given. A further issue in the theoretical simulations is the contact resistance and hysteresis effects. The state of the art extraction method of the contact resistance is the so called transfer line method (TLM) where a (constant) contact resistance is determined by extrapolation to zero channel length from electrical device characterization with different channel length. This method turned out to give rather a rough approximation when compared to experimental results of numerous NIL-devices with different channel lengths on different dielectric materials. Therefore an improved transfer line method (iTLM), where a channel length dependent contact resistance is considered, was developed. 
The temperature dependent device characterizations were focussed on the investigation of organic thin film transistors with pentacene as the active materials. We investigated the temperature dependence of the hole mobility and the threshold voltage for a large number of devices with different channel length. The majority of the temperature dependent measurements were performed with liquid N2 as the coolant. For one set of experiments the capability of liquid He was tested. In the latter experiments, pentacene based devices has been investigated down to around 35 K. However, the highly reduced source/drain currents at these low temperatures did not deliver sufficient results in terms of signal-to-noise ratio.


The final issue in this project was the up-scaling of the nanoimprint process to larger stamp sizes of up to (2,5x2,5) inch2 with the scope of a future large scale device fabrication by using roll-to-roll technology. The main problems encountered in defect free imprinting with larger stamps were the alignment of source and drain electrode on structured gate and the mechanical stress loaded on the gate dielectric by the hot embossing. Both result in a poor yield already achieved with smaller stamps of (10x10) mm2. Therefore a completely new device geometry based on a self-aligned process was successfully evaluated. In this process nanoimprint lithography is the first step used to structure the gate electrode on a transparent substrate. The source/drain electrodes are structured by backside exposure through the nanoscaled gate. An additionally applied photomask defines the conducting paths as well as the contact pads in the same process step with relatively broad alignment tolerances. Due to the restricted availability and high costs of large area stamps with sub-µm resolution the silicon master was finally fabricated directly at Joanneum Research by using a novel photolithographic prototyping procedure.